1. Field of the Invention
The present invention generally relates to a clock signal generation circuit, and particularly to a clock signal generation circuit for generating a multiphase clock signal used for a sample hold circuit (hereafter referred to as “S/H circuit”) for interleave operations.
2. Description of the Related Art
In conventional multiphase clock signal generation techniques, there has been used a clock signal generation circuit which compares delay values of three clock signals in a predetermined combination of clock signals φ1 to φ8 of eight phases and which controls delay values of the clock signals φ1 to φ8 in accordance with the comparison result. (For example, refer to Non-patent Document 1: Technical Digest p. 396, p. 397, and p. 470 of International Solid-State Circuit Conference of US Institute of Electrical and Electronics Engineers in February, 2001).
However, in the conventional interleave operations of interleave S/H circuits, there is a problem of a skew which occurs as a deviation caused in a timing of a clock signal for controlling a sampling switch from an ideal value in timing of the clock signal, and therefore a harmonic distortion undesirably occurs and an SNDR (Signal to Noise and Distortion Ratio) is deteriorated.
FIG. 11 is a graph showing a relation between a skew σ and a SNDR in the case of an input signal frequency of 50 MHz and a sampling frequency of 100 MHz. As shown in FIG. 11, even when a sampling frequency is 100 MHz and a resolution of an A/D converter connected after an S/H circuit is 10 bits, it is necessary to suppress a skew value to 2 ps or less. However, in the conventional multiphase clock signal generation circuit, it is impossible to decrease the skew value to 2 ps or less.